One year with an iPSC/860

This paper describes experiences over the past year with an the Intel iPSC/860, a distributed memory MIMD parallel computer based on the Intel i860 oat-ing point processor. The system at NASA Ames Research Center has 128 nodes, and a theoretical peak performance of over seven GFLOPS. This paper describes the system at Ames Research Center, talks about system stability, compiler performance measured by the NAS kernels, and results from a two-dimensional computational uid dynamics application. In spring of 1989 DARPA and Intel Scientiic Computers announced the \Touchstone" project. This project calls for the development of a series of prototype machines by Intel Scientiic Computers, based on hardware and software technologies being developed by Intel in collaboration with research teams at CalTech, Illinois. One of the milestones is the \Gamma" prototype. On December 29, 1989, the Numerical Aerodynamic Simulation (NAS) Systems Division at NASA Ames Research Center took delivery of one of the rst two Intel Touchstone Gamma prototypes. The system is marketed commercially as the Intel iPSC/860 and will be referred to as the iPSC/860 for the remainder of the paper. For a review of early experiences with the iPSC/860 at Ames Research Center and Oak Ridge National Laboratory, see 1] and 5] respectively. The iPSC/860 system is based on the 64 bit i860 microprocessor by Intel 6]. The i860 runs at 40 MHZ (the initial system was delivered with 33 MHZ processors , which were upgraded to 40 MHZ). The theoretical peak speed is 80 MFLOPS for 32 bit oating point and 60 MFLOPS for 64 bit oating point operations. There are thirty-two 32-bit integer address registers, and sixteen 64-bit oating point registers (which may be used as thirty-two 32-bit oating point registers). Floating point register 0 is hardware wired to zero. This implies there are only fteen 64-bit oating point registers that can hold non-zero values. The i860 also has an 8 kilobyte data cache and a 4 kilobyte instruction cache on-chip. The data path between cache and registers is 128 bits wide. The data path between main memory and registers is a 64 bits wide. The i860 has a number of features to facilitate high execution rates. First of all, a number of important operations, including oating point add, multiply, and loads from main memory, can be pipelined. When pipelined oating point operations are used, they are segmented into three stages, and a new operation can be …